The development of a computer graphics system creates the need for fast memories capable of storing huge amounts of data, such as 3-D graphics data. Among such memories are cached memories developed to improve DRAM main memory performance by utilizing a faster SRAM cache memory for storing the most commonly accessed data. For example, U.S. Pat. No. 5,566,318 discloses a cached DRAM that integrates a SRAM cache memory with a DRAM on a single chip. Sense amplifiers and column write select registers are coupled between the SRAM cache and the DRAM memory array. A column decoder is associated with the SRAM cache for providing access to the desired column of the SRAM. A row decoder is associated with the DRAM memory array to enable access to particular rows of the DRAM. Input/output control and data latches receive data from the SRAM to provide data output via data input/output lines. The current row of data being accessed from the DRAM memory array is held in the SRAM cache memory. Should a cache "miss" be detected, the entire cache memory is refilled from the DRAM memory array over a DRAM-to-cache memory bus.
In a conventional cached DRAM, separate pins are used to provide address and command signals. In particular, command pins are required to issue commands for supporting DRAM and SRAM operations. For example, a precharge pin may be used for supplying a DRAM row precharge command, a refresh pin may be used to provide a command for refreshing the DRAM. Separate pins may be used to define type and length of a data burst in a burst mode of operation. Also, several pins may be required to control masking and to provide mask data for masked write operations.
To minimize the number of pins on a cached RAM chip, it would be desirable to use address pins for supplying commands.